It is well known that extremely high voltages can develop in the vicinity of an integrated circuit due to the build-up of static charges. A high potential may be generated to an input or output buffer of the integrated circuit, which may be caused by a person touching a package pin that is in electrical contact with the input or output buffer. When the electrostatic charges are discharged, a high current is produced at the package nodes of the integrated circuit, and is referred to electrostatic discharge (ESD). ESD is a serious problem for semiconductor devices since it has the potential of destroying the entire integrated circuit.
The duration of the ESD transient is very short, typically in the order of nanoseconds, and the conventional circuit breakers cannot react quickly enough to provide adequate protection. For this reason, it has become a known practice to incorporate ESD devices in integrated circuits. Conventionally, bi-directional diode strings were coupled between the package pins to protect the respective circuit. Other ESD devices such as transistors were also used. The ESD devices were also widely used between power lines to protect the internal circuits coupled between power lines and to discharge ESD currents to the ground.
FinFET is the most attractive candidate for sub N32 technology. To make the process for forming ESD devices compatible with the formation of FinFET structures, FinFETs were conventionally used to construct the ESD protection circuits, wherein the channels of the ESD FinFETs were used for conducting ESD currents. This approach, unfortunately, faces design and process issues. First, to provide a high ESD protection capability, a great number of FinFET devices, sometimes as many as over 10,000 FinFETs, were connected in parallel. This means that the breakdown of any one of these finFETs may cause the entire ESD protection circuit to mal-function. One way for solving this issue is to make all FinFETs identical, so that they can be turned on simultaneously. However, due to process reasons, this is very difficult to achieve. To solve this problem, a RC network may be used to bias the gates of the ESD FinFET devices, as is shown in FIG. 1, wherein resistor R1, capacitor C1, and inverter Inv1 are provided to bias FinFET 2. The output of inverter Inv1 is connected to gate 4 of FinFET 2. Vdd is connected to the drain, and Vss is connected to the source of FinFET 2. With the bias voltage applied on the gate of ESD FinFET 2, FinFET 2 is unlikely to go into the snapback mode, and hence more ESD FinFETs can be tuned on simultaneously. However, the RC network itself occupies large chip area and may result in false actions during a normal operation mode. Thus, the RC network is only suitable for power clamps, not for I/O protections.
Accordingly, what is needed in the art is an ESD protection device whose formation process is compatible with the formation of FinFETs while at the same time overcoming the deficiencies of the prior art.